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S Jul 4, 2017 at 19:01 history suggested user788 CC BY-SA 3.0
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Jul 4, 2017 at 18:45 review Suggested edits
S Jul 4, 2017 at 19:01
Sep 12, 2016 at 15:20 comment added Karl The 8086 is a 16 bit computer, as is the 8088, which is an 8086 limping along with an 8 bit memory bus. And forget 5 MHz, you'll be lucky if you can get to 100 kHz with all the capacitance and inductivity in the miles of wiring you'll need. 30000 transistors for the 8086, plus 6.4 million more for 200*8 kbit of SRAM (4 transistors for each bit).
Sep 12, 2016 at 12:32 comment added Magic-Mouse Well basically it ends up being the production force of 20 people making makeshift transistors for 12 hours a day
Sep 12, 2016 at 12:25 comment added Luaan I don't mean just the complexity of design. It takes a lot of transistors to get that functionality. Sure, part of the reason this wasn't used in the past was that it a) wasn't cost effective, b) was hard to design. But cost-effective applies in our scenario as well - there's a difference between making a homebrew CPU with 5000 transistors, and 5 million transistors. We can't make a better 8086 today - all the improvements since (beyond making the transistors smaller and faster - not applicable in our scenario) were huge shifts in the whole design of the CPU.
Sep 12, 2016 at 12:15 comment added Magic-Mouse @Luaan you are confusing old components with making something "new from scratch" with primitive tools, we have advanced computers who can calculate and design the system, beforehand. "The group would know exactly how to find and assemble any items involved in the process of creating the machine." So the problem here is finding components in nature and assemble it, it says nowhere that they could not have CAD and or calculated strategy with them.
Sep 12, 2016 at 12:13 comment added Luaan @MolbOrg Yup, but that's very complex. You need at least some measure of out-of-order execution (very complex), some cache allocation strategy, cache transparency etc. The 8086 had no on-chip cache, and it was already pushing the limits of the technology Intel had at the time. Suddenly, your 5000 transistors doubled, even when not counting the transistors you need for the onboard cache in the first place. And that might be an optimistic estimate :D
Sep 12, 2016 at 12:09 comment added Luaan No, you're missing my point. Just the electricity lag would be enough to discount anything above ~10 MHz (synchronous, of course - there's a lot more you can do with asynchronous, but that makes the whole system much more complicated). That's before it gets to the transistors, and assuming optimal addressing (in practice, you would need much more than just the 10 meters of wiring to address anything in the huge memory core). And how much memory could you fit in a cube of 10m? If it takes a cubic cm (generous) to store one bit, you get about 1 MiB - ignoring all the addressing circuits etc.
Sep 12, 2016 at 12:09 comment added MolbOrg @Luaan make L1 L2 cache, program it wise to minimize border crossing, But yes I missed the point initially.
Sep 12, 2016 at 12:03 comment added Magic-Mouse "you're already pushing the limits at 10 MHz" - ofcause i am. we are talking about hand crafted components versus. high accuracy IC-components. I also just rated it plausible within 5 years, not possible.
Sep 12, 2016 at 12:03 comment added Luaan @Molborg Yes, memory was faster than CPUs for a time (this was still true at the time of the Windows 1.0). That's why I'm noting that in Magic Mouse' computer, it would already be the other way around. And I wasn't talking about frequency on the cable, but on the CPU - note how I'm talking about latency in the communication. If the CPU doesn't have out-of-order processing, it must wait on memory on each memory operation, which puts a limit on how fast the memory must be not to impede the CPU. Not a big deal for calculation, very much a big deal for Windows.
Sep 12, 2016 at 11:45 comment added MolbOrg @Luaan twisted pairs working at higher distances then 10m with frequencies you mention.
Sep 12, 2016 at 11:43 comment added MolbOrg can confirm @Magic-Mouse , as I dug history, saw statements that memory at first was faster then cpus (not totally strong confirmation but)
Sep 12, 2016 at 11:18 comment added Luaan First, you need to take into account how many transistors are in a series in any given operation - as a very rough estimate, you can only afford logic that uses less than sixty transistors in a series per operation to keep the 5 MHz, and that's already ignoring the paths between the transistors. Second, don't forget latency. Even if your memory could operate at 300 MHz, it doesn't help much if it takes 20 CPU ops to get data to the CPU. Ignoring the transistors, if your memory is 10 meters far from the CPU, you're already pushing the limits at 10 MHz.
Sep 12, 2016 at 9:09 comment added Magic-Mouse A computer in 1985 runs at about 5-8 Mhz, with the transistors switching capability of 300 MHz you got a 150% overhead on that account, i don't really thing that would be the bottle neck.
Sep 12, 2016 at 9:06 comment added Luaan The problem is that big size means slow operation. Making a CPU fast enough for Windows 1.0 isn't too big of a deal, even from simple-to-make TTL chips; it might even be doable with discrete components. However, making memory fast enough for Windows 1.0 is a problem - exactly because of the size required. Note how the silicon area of any modernish computer is dominated by memory (DRAM and SRAM). The propagation of electricity is too slow to maintain the speed you need.
Sep 12, 2016 at 8:46 comment added Magic-Mouse Yes, i did write that it would take a lot of space didn't i?
Sep 12, 2016 at 8:25 comment added Luaan RAM is actually quite a big deal. The problem isn't making a bit of memory (SRAM is very simple, really). The problem is making a lot of memory - even Windows 1.0 required almost 200 kiB of memory. That's huge.
Sep 12, 2016 at 6:37 history answered Magic-Mouse CC BY-SA 3.0