Timeline for Is this timeframe realistic for compact full-brain simulation?
Current License: CC BY-SA 4.0
10 events
| when toggle format | what | by | license | comment | |
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| Jan 28 at 21:25 | comment | added | KEY_ABRADE | I stand corrected. | |
| Jan 28 at 21:22 | comment | added | Pelinore | @AlexP Ta [thumb] | |
| Jan 28 at 21:21 | comment | added | AlexP | @KEY_ABRADE: The 5 nm process does not make 5 nm transistors, not even close. See the nice Wikipedia article which kindly provides physical sizes; for example, transistor gate pitch remains somewhere around 50 nm, and a (four-transistor) SRAM bit-cell is about 150 by 150 nm. | |
| Jan 28 at 21:13 | comment | added | Pelinore | Hmm (again) The term "2 nanometer" or alternatively "20 angstrom" (a term used by Intel) has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors I'm not so sure now that you have anything there ;) will have to dig deeper but that doesn't sound promising for your comment @KEY_ABRADE | |
| Jan 28 at 20:32 | history | edited | Pelinore | CC BY-SA 4.0 |
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| Jan 28 at 20:30 | comment | added | Pelinore | Hmm .. I'll have to stop editing and do some more current reading .. cheers for the comment > after one last small edit to take the sting out of the last bit ;) | |
| Jan 28 at 20:28 | comment | added | KEY_ABRADE | OP noted that "processing power progresses according to Moore's law until transistor size reaches the size of an atom, at which point it can progress no further", which implies they aren't sticking to Moore's law all the way. Moreover, TSMC is producing 3 nm transistors and plans to produce 2 nm transistors, which suggests quantum tunneling is not a hard barrier to sub-5 nm transistors. | |
| Jan 28 at 20:21 | history | edited | Pelinore | CC BY-SA 4.0 |
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| Jan 28 at 20:15 | history | edited | Pelinore | CC BY-SA 4.0 |
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| Jan 28 at 20:07 | history | answered | Pelinore | CC BY-SA 4.0 |